Comparison of Adders for optimized Exponent Addition circuit in IEEE754 Floating point multiplier using VHDL

Floating point arithmetic has a vast applications in DSP, digital computers, robots due to its ability to represent very small numbers and big numbers as well as signed numbers and unsigned numbers. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Here we compare three different types of adders while calculating the addition of exponent bits while calculating the single precision and double precision floating point multiplication. We also present the multiplication of mantissa/significand bits by decomposition of operands method for IEEE 754 standard multiplication. Here we break down the mantissa bits of each single precision floating point operand into 4 Parts, each of six bits. Likewise we breakdown the mantissa bits of double precision floating point operand into 4 Parts, 3 parts of 13 bits each and one part of 14 Bits. We get 16 partial product terms in each case. Careful addition of these partial product terms are required to get the product of mantissas.